FLYNN'S CLASSIFICATION (cont)

Hierarchy of generic computer system:

APPLICATION

OPERATING SYSTEM

SYSTEM PROGRAM / COMPILER

COMMUNICATION / NETWORKING

ADDRESS SPACE

INSTRUCTION SET ARCHITECTURE

HARDWARE

 

While transforming from single instruction single data (SISD) to single instruction multiple data (SIMD) OR multiple instruction single data (MISD) OR multiple instruction multiple data (MIMD),

almost every layer of computer system hierarchy gets affected.

SISD, SIMD, MISD and MIMD  ,all involves the variations of the VON-NEWMEN concept.

 Chipset:

A chipset is a set of electronic components in an integrated circuit that manages the data flow between the processor, memory and peripherals. Because it controls communications between the processor and external devices, the chipset plays a crucial role in determining system performance.

There are two chips in the core logic chipset :

è Northbridge  - implements faster capabilities of the mother board in a chipset computer architecture.

è Southbridge  - typically implements the slower capabilities of the motherboard in a chipset computer architecture.

 

Multiple Instruction Single Data :

 

It is a type of parallel computing architecture where many processing units(PUs) perform different operations on the same data.

 

  In the above block diagrram, we have multiple instructions IS1,IS2,IS3 given to 

individual control units which are further connected to processing units.There are latches between each processing unit which stores the data being processed by the previous stage.

 

Lets take an example of image processing:

 

Suppose we are having 3 instructions as decreasing the intensity of the image(IS1),encoding a message int the image(IS2) and then decreasing the size of the image(IS3).

All the instructions are given to CUs parallely. Data of image is taken by PU1 from main memory  and IS1 is processed. The processed data is then stored in the latch provied after PU1. In the meanwhile data is being saved, data of next image start transferring to PU1. The data present in first latch is processed in PU2. The process goes on until nall the data is being processed. 

 

 The above example shows that there is a kind of pipelining being used in data processing.

 

A systolic array is an example of a MISD structure.

Systollic arrays : It is a pipe network arrangement of processing units called cells. It is a specialized form of parallel computing, where cells (i.e. processors), compute data and store it independently of each other. Each cell shares the information with its neighbours immediately after processing.

 

Multiple Instruction Multiple Data :

MIMD is a technique employed to achieve parallelism. Machines using MIMD have a number of processors that function asynchronously and independently. At any time , different processors may be executing different instrucyions on different pieces of data. MIMD  machines can be either of shared memory or distributed memory categories.

 

Shared memory models :

The processors are all connected to globally available memory . The OS usually maintains the coherence.

Examples of shared memory multiprocessors are :

1.       NUMA (Non uniform memory access) :  Under NUMA a processor can access its own local memory faster than non-local memory. The benefits of NUMA are limited to particular workloads, notably on servers where the data are often associated strongly with certain tasks or users.

2.       UMA (Uniform Memory Access) :  All the processors share the physical memory uniformly. In a UMA architecture, access time to a memory location is independent of which processor makes the request or which memory chip contains the transferred data.

 

Distributed memory models :

In distributed memory MIMD machines, each processor has its own individual memory location. Each processor has no direct knowledge about other processor's memory. For data to be shared, it must be passed from one processor to another as a message.

Example – NORMA (No remote memory access) :
Accesses to remote memory modules are only indirectly possible by messages via interconnection network .

MIMD machines may have combination of both the above memory models . The independent UMA clusters may communicate via Global InterConnection similar to a NORMA.

 

Questions to  ponder upon :

 

1)      Is this maximum parallelism we can achieve ?

2)      Can we get rid of von-newmen concept?

3)      How to decompose a program?

4)      Relationship between architecture and application.

 

By Shefali Singh and Upasana Mehta