Uniprocessor parallelism

Yesterday i had a small conversation with ma'am and got my doubts clear. 

This may be helpful for you too, so posting it here.

I have a question , if we are talking about architectures then pipeline, superpipeline ,  superscalar where should these come . They are not architectures ,they are some some techniques which can be used to increase DOP . And i think we can use these techniques within any architecture m i rite ??

(this was my question)

reply by ma'am ,

Pipelining per se is indeed a technique.The basic idea is to achieve temporal parallelism by overlapped operations.  

But pipelined architecture is not a misnomer - Any feature that helps instructions to flow from one point of the hardware to another qualifies for a distinct architecture. Just think of architecture as the ISA plus the roadways for instructions and data to flow. 

That way, pipelined architecture determines how they flow within a single microprocessor. You are right - all three versions (P/L, superP/L and superscalar P/L) increase DOP, but within one processor. You can think of them as parallelism within a uni-processor. Hence they all support fine-grain Instruction Level Parallelism (ILP).

That decides where they come in architectures. Write them under uniprocessor parallelism. 

You can make a complete classification for uniprocessor parallelism. 

1) CISC:

- Pipelined, microcoded, Implicit parallelism. Earlier, CISC architectures were NOT pipelined but now any high performance processor (barring say 8086, 6800, etc) are pipelined.

- Simple compiler. 

- Parallelism mostly detected implicitly at run time by hardware support, but compiler optimizations also help. 

2) RISC: 

- Pipelined,hardwired control, Implicit parallelism. 

- Simpler hardware than CISC.

- But need more compiler support.

- Parallelism is detected mostly implicitly, but compiler support needed.

3) RISC at core but CISC outside:

- Pipelined, control unit uses trace cache for frequently used simpler instructions+ microcode ROM for occasional complex instructions, Implicit parallelism.

- Parallelism mostly detected implicitly at run time by hardware support but compiler optimizations help. 

  

4) VLIW:

- Pipelined, horizontally microcoded, Explicit parallelism. 

- Even simpler hardware than RISC.

- But need even higher compiler support. 

-Parallelism detected explicitly by compiler but hardware support helps.

Note All four architectures can be superpipelined & superscalared.

By:-

Uzma