CACHE COHERENCE AND SNOOPY BUS PROTOCOL

In computing, cache coherence refers to the consistency of data stored in local caches of a shared resource. When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system. In a memory hierarchy for a multiprocessor system, data inconsistency may occur between adjacent levels or within the same level. For example, the cache and main memory may contain inconsistent copies of the same memory block because multiple processors operate asynchronously and independently. When multiple processors maintain locally cached copies of a unique shared-memory location, any local modification of the location can result in a globally inconsistent view of memory. Cache coherence schemes prevent this problem by maintaining a uniform state for each cached blocks of data.

SNOOPY BUS PROTOCOL

In computing a snoopy cache is a type of memory cache that performs bus sniffing. Such caches are used in systems where many processors or computers share the same memory and each have their own cache. Snoopy protocols achieve data consistency among the caches and shared memory through a bus watching mechanism.

There are 2 basic approaches

1.    write-invalidate – invalidate all other cached copies of a data object when the local cached copy is modified (invalidated items are sometimes called "dirty")

2.    write-update – broadcast a modified value of a data object to all other caches at the time of modification

Snoopy bus protocols achieve consistency among caches and shared primary memory by requiring the bus interfaces of processors to watch the bus for indications that require updating or invalidating locally cached objects

 

 

Cache consistency by bus watching mechanism

• Each cache watches bus for write operations
• Write through: forward write immediately to memory
• Write-invalidate: cache copies are invalidated.
• Write-update: cache copies are updated.
• Disadvantage: high bus traffic.
• Copy back: write modified cache line only back if

1. Line needs to be replaced, or
2. Another processor reads data.

 

 

 

Initial state consistent caches

 

 

After Write-Invalidate by P₁

After Write-Update by P₁

 

Sources:

http://www.risc.jku.at/education/courses/ws97/intropar/architectures/index_5.html

http://www.icsa.inf.ed.ac.uk/research/groups/hase/models/coherence/

http://www.info425.ece.mcgill.ca/lectures/L28-SnoopyCoherence.pdf

 

 

 

 

Varun Singla 363/CO/11